Microcircuit generator of tone dtmf signals. Study of the receiver and transmitter of dtmf signals. Dtmf signal conditioning

The topic of simple devices, I decided to build a DTMF signal generator for the same ATtiny2313. Who does not know, DTMF (English Dual-Tone Multi-Frequency) is a two-tone multifrequency analog signal used for dialing phone number... Read Wikipedia.

The decision to assemble such a device was dictated by the desire to try to implement complex analog signals using a microcontroller. No practical application for this device was not planned, but can anyone use such a device? Use it!

DTMF generator source

Now let's see what we got.

The signal is formed using PWM and in order to give it the desired shape, an RC chain is used. As a result, after the RC chain, we get the following signal (button 6 is pressed):

Along the entire curve of the useful signal, we observe a high frequency comb (the frequency is higher than the audible one, so it will not create noise) - this is the work of the RC chain. You can make the line smoother by increasing the capacitance of the capacitor or the resistance of the resistor, but in this case, the swing of the useful signal will significantly decrease.

We look at the signal spectrum and make sure that there are two individual frequencies(the PWM frequency has gone beyond the display area), then everything is fine - the device is working as it should.

Ready-made solutions

For the tasks of generating and decoding a DTMF signal, there are ready-made solutions... Here are a couple of datasheets for these microcircuits.

DTMF generator
- DTMF decoder

P.S. It's a pity there is no ADC in ATtiny2313 - you could have also freaked out the DTMF decoder! But nothing, I will repeat it on mega, I will definitely attach it.

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The invention relates to the field of digital generation of two-tone frequency (DTMF) signals intended for data transmission, for example, in the field of telephony. The achieved technical result is a decrease in the number of redundant circuit elements, an increase in economic efficiency. The DTMF signal generator, which implements the DTMF signal generation method, contains two accumulators, two latching registers, two memory devices, a final adder, a digital-to-analog converter, a converter of DTMF signals in a sequence of integers, a divider of the master frequency of a DTMF signal generator with an adjustable division factor, a converter DTMF codes into the division factor code. 2 sec. and 3 c.p. f-ly, 2 dwg.

The invention relates to methods for digital generation of DTMF (two-tone frequency) signals intended for data transmission, for example, in the field of telephony with tone-frequency dialing. The closest in technical essence and the achieved result to the claimed method is the method for generating DTMF signals, presented in US patent No. 5034977 from 04.04.89, publ. 07/23/91, M.cl. 5 H 04 M 1/00. A known method for generating DTMF signals includes the selection of the first and second codes of sampling angles corresponding to the first and second frequencies of the DTMF signal components, cumulative summation of the first and second codes of sampling angles, respectively, periodically fixed, with a period corresponding to the clock sampling frequency, the first and second results of the cumulative summation, obtaining the first and second discrete values of the DTMF signal components stored in the address located cells of the corresponding tables of the discrete values of the DTMF signal components, by reading from the corresponding tables at the addresses corresponding to the results of the cumulative summation of the sampling angle codes, summation the first and second discrete values of the DTMF signal components to obtain the third discrete value corresponding to the DTMF signal value. The known method of generating DTMF signals is as follows: depending on the DTM code F signal by means of the first conversion of DTMF signal codes, the first code is selected, which determines the sampling angle of the signal with a frequency corresponding to the group treble- columns, and by means of the second conversion of DTMF signal codes, the second code is selected, which determines the sampling angle of the signal with a frequency corresponding to the group of low frequencies - rows, periodically, with a period corresponding to the sampling clock frequency, the first sampling angle code is summed in the corresponding accumulator and fixed in the corresponding register, the output of which is the result, the value of which corresponds to the address of the table cell stored in the corresponding read-only memory and in which the corresponding discrete values of the sines are located, which determine the upper frequency of the DTMF signal in the same way, periodically, with a period corresponding to the clock sampling frequency, the second code of the sampling angle is summed up in the corresponding accumulator and fixed in the corresponding register, the output of which is the result, the value of which corresponds to the address of the table cell stored in the corresponding read-only memory and in which the corresponding discrete values of the sines that determine the lower frequency of the DTMF signal are located, the discrete values of the sines that determine the upper and lower frequencies of the DTMF signal are summed in the final adder, determining the discrete value of the DTMF signal and through digital-to-analog conversion are fed to the output, forming stepwise - sinusoidal DTMF signal corresponding to the input code of the DTMF signal. The known method is ineffective due to its low technical and economic indicators and technological indicators. Technical and economic indicators are determined by the necessary costs when implementing the method to achieve required parameters presented to DTMF signals. V known method the frequency generation accuracy depends on the bit depth of the code corresponding to the sampling angle, which requires a large bit capacity of the accumulator, which complicates the implementation of the method with simple hardware. Namely, the code of the sampling angle in the known method is determined by the expression K = (F / F t) 32 ..., (1.1) where K is the code corresponding to the sampling angle; F is the generated frequency; F t is the sampling frequency. As you can see, the accuracy of the generated frequency unambiguously depends on the ratio of the generated frequency and the sampling frequency. 8 bits, and for high frequencies at least 9 bits, and for cumulative summation, respectively, at least 12 bits, which leads to an increase in the number of component elements of devices that implement the known method. Known devices for implementing the known method, namely adders, registers, read-only memories, have inputs / outputs with a width of 4 and 8 bits. Therefore, with a higher bit depth, additional technical and economic costs are required for the implementation of equally functional devices. At the same time, in the known method, a decrease in the number of digits after the decimal point leads to a frequency error exceeding the permissible one. Technological indicators are determined by the versatility and unification in the implementation of the method, for example, the current state of the art, which implies a decrease in material consumption, component elements and an increase in the multifunctionality of devices, requires the use of microcontrollers. Widespread microcontrollers used in telephony and telemetry measurements use 8-bit data and an 8-bit arithmetic-logic device, which requires additional computational operations related to data summation with a width of more than 8 bits and analysis of the carry signal when implementing the known method. which increases the number of commands and, accordingly, the clock frequency of the microcontroller, as well as the volume random access memory microcontroller, which leads to an increase in the cost of devices using a known method for generating DTMF signals. This conclusion is given when analyzing the application of the known method in a tone dialer based on microcontrollers manufactured by Atmel, Microchip tnc, etc. Thus, the known method is fundamentally ineffective, due to low technical and economic indicators, expressed in increased material consumption, energy consumption, and low technological indicators , since it has limitations when using the method, including in the composition of microcontrollers of widespread use, which is expressed in increased technical characteristics applied to microcontrollers, which reduces their versatility. The closest in technical essence and the achieved result to the claimed DTMF signal generator is the DTMF signal generator presented in US patent No. 5034977 from 04.04.89, publ. 07/23/91, M.cl. 5 H 04 M 1/00. The known DTMF signal generator includes: the first accumulator, the first latching register, the first memory device, the second accumulator adder, the second latching register, the second memory device, the final adder, the digital-to-analog converter, and the output of the first accumulator is connected with the input of the first latching register, the output of the first latching register is connected to the input of the first memory device, as well as to one of the inputs of the first storage adder, the output of the first memory device is connected to one of the inputs of the final adder, the output of the second storage adder is connected to the input of the second latching register, the output of the second latching register is connected to the input of the second storage device, as well as to one of the inputs of the second storage adder, the output of the second storage device is connected to the other input of the final adder, the output of the final adder is connected to the input of the digital a log converter, the output of which is the output of a DTMF signal generator. The known generator also contains a first converter of DTMF signal codes into the corresponding codes of sampling angles corresponding to the high frequencies of the DTMF signal, a second converter of DTMF signals codes into the corresponding codes of sampling angles corresponding to the lower frequencies of the DTMF signal, and the output of the first converter of DTMF signals is connected to another input of the first accumulator, the output of the second converter of DTMF signals is connected to another input of the second accumulator, the inputs of the first and second converters of DTMF signals are inputs of the DTMF signal generator, and the clock inputs of the first and second latching registers interconnected and are the entrance clock frequency DTMF signal generator sampling. The well-known DTMF signal generator provides a low technical result due to the excess number of circuit elements associated with different, as well as the excess capacity of the same functional elements. In addition, the implementation of the known technical solution is effectively possible in the form of a separate integrated microcircuit, but this requires the organization of specialized production, but given that DTMF signal generators are part of multifunctional devices (telephones with advanced capabilities, devices for transmitting telemetric information via telephone lines etc.) currently implemented on the basis of universal microcontrollers , the production of individual microcircuits of DTMF signals is economically ineffective. The basis of the proposed technical solution is the task of creating a method for generating DTMF signals using a DTMF signal generator, in which, by changing the conditions and sequence of operations, the method is implemented with high technical and economic indicators due to a decrease in the bit capacity of the same type operations, high technological indicators, when implementing the method, both in circuit design with simple hardware, and as part of a multifunctional microcontroller, associated with the repeatability, when implementing, of the same functional elements. The technical solution is based on the task of creating a DTMF signal generator, in which by the introduction of new elements and the implementation of new connections increases the technical result associated with a decrease in the number of redundant circuit elements, and accordingly increases the economic efficiency The problem is solved by the fact that in the known method for generating DTMF signals, including the selection of the first and second codes of the sampling angles corresponding to the first and second frequencies of the DTMF signal components, the cumulative summation of the first and second codes separately sampling angles with respectively periodically fixed, with a period corresponding to the sampling clock frequency, the first and second results of cumulative summation, obtaining the first and second discrete values of the DTMF signal components stored in the address located cells of the corresponding tables of discrete values of the DTMF signal components by reading from the corresponding tables by the addresses corresponding to the results of the cumulative summation of the sampling angle codes, the summation of the first and second discrete values of the DTMF signal components to obtain the third discrete value The value corresponding to the DTMF signal value is new in that the receipt of the first and second discrete values of the DTMF signal components stored in the address-located cells of the corresponding tables of discrete values of the DTMF signal components is performed by reading from the corresponding tables at the addresses corresponding to the results of the cumulative summation, respectively, of the first and the second sequences of integers, the average value of which corresponds to the codes of the sampling angles corresponding to the components of the DTMF signal. In addition, the averaged value of the sequence of integers forming the result of the cumulative summation can be the arithmetic mean of these numbers. In addition, the periodic recording of the first and second results of the cumulative summation can be with a period corresponding to the sampling clock frequency, different for different DTMF signals. is also solved in that the known DTMF signal generator, including the first accumulator, the first latching register, the first memory, the second accumulator, the second latching register, the second memory, the final adder, the digital-to-analog converter, and the output of the first accumulator is connected to the input the first latching register, the output of the first latching register is connected to the input of the first memory device, as well as to one of the inputs of the first accumulator, the output of the first memory device is connected to one of the inputs into the final adder, the output of the second accumulator is connected to the input of the second latching register, the output of the second latching register is connected to the input of the second memory device, as well as to one of the inputs of the second accumulator, the output of the second memory device is connected to another input of the final adder, the output of the final adder is connected to the input of the digital-to-analog converter, the output of which is the output of the DTMF signal generator, new according to the invention is that the DTMF signal generator additionally contains a converter of DTMF signals in a sequence of integers, a divider of the master frequency of the DTMF signal generator with an adjustable division factor, a code converter DTMF signals into the division ratio code, and the first output of the DTMF signal converter in a sequence of integers is connected to another input of the first accumulator, the second output of the DTMF signal converter in the sequence of integers is connected to another input of the second accumulator, the output of the master frequency divider of the DTMF signal generator with an adjustable division ratio is connected to the clock input of the converter of DTMF signals in the sequence of integers, as well as to the clock input of the first holding register and the clock input of the second holding register, the output of the converter of DTMF signals to the division factor code is connected to the input for setting the division factor of the master frequency divider of the DTMF signal generator, the input of the master frequency divider of the DTMF signal generator with an adjustable division factor is the input of the master frequency of the DTMF signal generator, the input of the converter of DTMF signals to the division factor code connected to the input of the converter of DTMF signals in a sequence of integers and is the input of the DTMF signal generator. In addition, the converter of codes DTMF signals in a sequence of integers can be made in the form of a controlled programmable memory, the memory of which consists of, corresponding to the number of DTMF signals, memory areas, consisting of corresponding to the length of the sequence of integers, memory cells, made so that in one half of the memory cell stores a number related to the first sequence of integers, and the other half of the memory cell stores a number corresponding to the other sequence of integers, which are the summands of the respective accumulators, and the programmable memory control is made with the possibility of separate selection control areas of memory and a separate memory cell. New features of the method for generating DTMF signals and the DTMF signal generator in combination with the known features of these objects provide new technical properties of objects, and, as a consequence of these properties, provide a new necessary technical result is produced. The causal relationship between the set of features of the proposed method and the achieved technical result is explained as follows. To reveal the essence of the proposed technical solution, the following calculations will be convenient: y (P) = sin (n) (1.2), where y (P ) is the discrete value of the sine function; = wT = 27F / Fr (1.3) is the sampling angle, measured in radians; n is the ordinal number of the sample - sample; F t = F OSC / kd is the sampling clock frequency, where F OSC is the setting frequency device; kd - adjustable division ratio. Then = 2FK D / F OSC. (1.4) As is well known, the sine function is periodic with a period of 2. To convert the sampling angle from radians to relative units and obtain the sampling angle code, we divide the entire period into m parts, where m is a binary integer. Thus, we get one minimum discrete part of the period: = 2 / m. (1.5) The sampling angle code is the relative value of the sampling angle in accordance with one part of the period, namely, K = / = 2F / F t: 2P / m = Fm / F t. (1.6) For example, for the generated frequencies 1477 Hz and 697 Hz (corresponds to the DTMF code of the signal “3”), at m = 64, and the clock frequency F t = 32768 Hz K 697 = 1.36; K l477 = 2.88. Obviously, for the binary display of the sampling angle code K 697 = 1.36 v, respectively 136 requires 8 bits (1281 + 640 + 320 + 160 + 81 + 40 + 20 + 10), and K 1477 = 2.88 v respectively 288 requires 9 bits (2561 + 1280 + 640 + 321 + 160 + 80 + 40 + 20 + 10). In this case, for the cumulative summation, respectively, in the binary representation, 12 bits are required, which determined the above-described disadvantages of the known solution. The proposed technical solution defines, for example, the number 1.36 as the average value of a sequence of integers 1 and 2, namely 1.36 = (1x + 2y) / (x + y), where x and y are the number of numbers 1 and 2, respectively , periodically repeated with a period (x + y). The value of the sampling angle code consists of an integer part Ts and a fractional part, i.e. for example 1.36 = 1 + 0.36. The relative accuracy of such a replacement in accordance with the expression (1.7) = K / C (1.7) increases with an increase in the integer part of the value of the sampling angle code. For example, for the generated frequency 697 Hz, m = 64, and the clock frequency F t = 32768 Hz, the error of replacing K 697 = 1.36 by the values of numbers 1 and 2 is 36 and 32%, respectively. At the same time, if we increase the value of m = 256, then the error of replacing K 697 = 5.45 with the values of the numbers 5 and 6 decreases by 9 and 10%, respectively. In this case, the error of the generated frequency, for example, when replacing K 697 = 5.45 by the values of the numbers 5 and 6 with a repetition period, equal to 16, 5.45 = (5x + 6y) / (x + y), where (x + y) = 16. Solving the equation, we obtain x = 9, y = 7, i.e. of sixteen accumulative summing operations, the term 5 is added nine times and the term 6 is added seven times, while in fact K 697 = 5.4375, substituting this value into expression (1.6) for m = 256, F t = 32768 Hz, we determine the actual calculated value of the generated frequency F = 696 Hz, while the error remained 0.1%. Thus, the cumulative summation of a sequence of integers, the average value of which corresponds to the corresponding sampling angles, makes it possible to achieve high technical and economic indicators by reducing the bit depth of cumulative summation operations due to the ability to vary components of the above expressions, and, accordingly, a decrease in the bit capacity of devices implementing the proposed method, which leads to a decrease in hardware and energy costs when implementing the method, and to ensure high technological performance of the proposed method when used in multifunction devices The causal relationship between the set of features of the proposed technical solution and the achieved technical result is explained as follows: The high technical result of the DTMF signal generator is ensured by the introduction of new elements of the DTMF signal code converter in a sequence of integers, the divider of the DTMF signal generator setting frequency with adjustable dividing factor, converter of DTMF signals codes into a divider factor code, which ensure the implementation of the method by circuit elements with the same bit width, not exceeding 8-bit, while there is no redundancy of elements necessary for solving several problems, for example, and for fixing the result of cumulative summation, and the same number of bits are used to address the corresponding storage device, implemented by no more than an 8-bit register, which can be performed by publicly available means in the form of one microcircuit or, in a microprocessor design, one memory cell. In addition, the implementation of storage adders can be performed in the form of identical devices, with the same bit capacity, in the form of publicly available adder microcircuits operating with 4-bit terms. that the numbers and, accordingly, the devices that form the above-described sequences of integers, the combination of which determines the corresponding codes of sampling angles, can be with a different bit depth, but the most optimal, from the point of view of fulfilling the goals set by the claimed solution, are 4-bit numbers. The technical result is also ensured when the proposed technical solution is implemented as part of microcontrollers, where the command system of microcontrollers necessarily includes commands operating with 4-bit numbers - nibbles. Thus, the proposed technical solution of the DTMF signal generator makes it possible to provide a high technical result associated with a decrease in the number of circuit elements, and also provides versatility in the implementation of the DTMF signal generator both by publicly available hardware and as part of multifunctional microcontrollers, which determines the high economic efficiency of the technical solution. depicts a DTMF signal generator that implements a method for generating DTMF signals. The DTMF signal generator includes a converter 1 of DTMF signals in a sequence of integers, a divider 2 of the master frequency of a DTMF signal generator with an adjustable division factor, a converter 3 of DTMF signals codes into a code division factor, the first accumulator 4, the first latching register 5, the first memory device 6, the second memory device 7, the second latching register 8, the second accumulator adder, the final adder 10, the digital-to-analog converter 11. The operation of the DTMF signal generator is illustrated by an example of the implementation of the method for generating DTMF signals. Based on expressions (1.4, 1.6) and technical data, in particular, the master frequency of the device where the proposed method will be implemented, sequences of integers are calculated that determine the corresponding codes of sampling angles, and dividing factor codes for the divider 2 of the master frequency of the DTMF signal generator with an adjustable dividing factor, which are written into the corresponding memory cells of the converter 1 of the DTMF signals in a sequence of integers and the converter 3 of the DTMF signals codes into the dividing factor codes, also pre-calculate the discrete values of the corresponding functions sines, the number of which is determined by the number of samples m, and are written into the corresponding memory devices 6 and 7, when generating a DTMF signal, at the inputs of converter 1 and converter 3, which are generator inputs, for a time of the DTMF signal, the code of the generated DTMF signal will be set, at the output of the converter 3 a code will be set that determines the division factor for the divider 2, while the output of the divider 2 will set the sampling clock frequency periodically, with a period corresponding to the sampling clock frequency, from the first output of the converter 1 there will be enter the input of the first accumulator 4 binary numbers included in the first sequence of integers, and from the second output of the converter 1 will enter the input of the second accumulator 9 binary numbers included in the second sequence of integers corresponding to the components of the DTMF signal, the results of accumulative summation are supplied from the outputs of the accumulative adders to the inputs of the corresponding latching registers 5 and 8, from the outputs of the latching registers 5 and 8, the results of cumulative summation, with a period corresponding to the sampling clock frequency, are fed to other inputs of the corresponding accumulators digital adders 4 and 9, as well as to the inputs of the corresponding memory devices 6 and 7, setting the addresses of the discrete values of the sines of the corresponding components of the DTMF signal, from the outputs of the memory devices 6 and 7, the discrete values of the corresponding components of the DTMF signal are fed to the corresponding inputs of the total adder 10, at the output of which a discrete binary DTMF signal is formed, which is fed to the input of the digital-to-analog converter 11, at the output of which a step sinusoidal DTMF signal is formed, corresponding to the input code of the DTMF signal. The converter 1 of the DTMF codes of signals in a sequence of integers (Fig. 1) can be made in the form shown in Fig. 2, where the converter of DTMF codes of signals in a sequence of integers includes a control device 12, a programmable memory 13. The operation of the DTMF signal generator is illustrated further on specific example implementation of the proposed method in a telephone tone-frequency dialer. Preliminarily, based on expressions (1.4, 1.6) and technical data, sequences of integers are calculated that determine the corresponding codes of sampling angles and codes of division factors for the divider 2 of the master frequency of the DTMF signal generator with an adjustable division factor. Considering that the implementation of the method includes the same type of calculations, then to illustrate the work in a specific example, the implementation of the method for generating a DTMF signal corresponding to pressing the "7" key as part of the tone-pulse dialer is given. As the master frequency of the generator set quartz frequency, the most common in telephone technology, namely F OSC = 3579545 Hz. Pressing the “7” key corresponds to a DTMF signal with the upper (columns) frequency of 1209 Hz and the lower (lines) frequency of 852 Hz. Since the DTMF signal simultaneously transmits two frequencies, the division coefficients are calculated for a higher - upper frequency so that the corresponding sampling angle code in accordance with expression (1.6) is close to the maximum value - 16, which is implemented in no more than 4-bits data. Thus, at F OSC = 3579545 Hz, the number of discrete values of sines m = 128, the calculated values of the division factor for the divider 2 of the master frequency of the DTMF signal generator with an adjustable division factor KD = 240 = 460, while the corresponding sampling angle codes for the upper frequency are K 1209 / 852 = 10.376, for the lower frequency K 852/1209 = 7.312 According to the invention, the sampling angle codes are replaced by a sequence of integers, respectively 10/11 and 7 / 8.10.375 = (10x + 11y) / (x + y), while actually K 1209/852 = 10.3757.312 = (7x + 8y) / (x + y), while actually K 952/1209 = 7.313, with (x + y) = 16. Thus, 10.375 is replaced by periodically a repeating sequence of integers 10 10 times and 11 6 times, and 7,312 is replaced as 7 11 times and 8 5 times. The memory area for the DTMF code of signal “7” in binary is as follows:
Thus, sixteen tables are calculated corresponding to the DTMF signal codes, namely 0, 1, 2 ... 9, *, #, A, B, C, D, and pre-recorded in the memory of the programmable memory 13 (converter of the DTMF character code into When you press a key, for example, “7” at the generator input, for the duration of the DTMF signal, the binary code of the DTMF signal “7” (0111) is set, the converter 3 of the DTMF signal code into the division factor converts the DTMF signal code into the coefficient code division kd for the divider 2 of the master frequency of the generator with an adjustable division factor, the output of the divider 2 will set the sampling clock F t = F OSC / KD. The DTMF code of the signal is also fed to the address inputs of the higher bits of the programmable memory 13 (converter of DTMF codes of signals in a sequence of integers) and is present there for the duration of the DTMF signal. The controlled device 12, made, for example, in the form of a counter (a converter of DTMF signals in a sequence of integers), under the influence of clock signals with a frequency of t, cyclically changes its value at the parallel outputs sequentially from 0000 to 1111, changing accordingly the values of the address inputs of the least significant bits of the programmable memory device 13 (converter of DTMF signals in a sequence of integers), 8-bit (byte) numbers appear at the output of a programmable memory 13 with a sampling clock frequency, while in accordance with Table 1, the most significant four bits (high nibble) form a sequence of integers , the collection of which, namely, the arithmetic mean, determines the code of the sampling angle corresponding to the upper (columns) frequency, and the lower four bits (lower nibble) form a sequence of integers, the collection of which, namely the arithmetic mean, determines the code the sampling angle corresponding to the lower (line) frequency, four-bit data, in accordance with Table 1, from the output of the programmable memory 13 (converter of DTMF signals in a sequence of integers) are separately fed to the inputs of the corresponding accumulators 4 and 9, at the outputs of the corresponding adders 4 and 9, the data changes with a sampling clock rate from 0 to m (in this case, m = 128), defining and fixing by means of latching registers 5 and 8 addresses for memory devices 6 and 7, in which the binary discrete values of the corresponding sinusoidal DTMF components are respectively written signal, from the outputs of storage devices 6 and 7, binary discrete values of the corresponding sinusoidal components of the DTMF signal are fed to the corresponding inputs of the final adder 10, at the output of which binary discrete values of the DTMF signal are formed, which are then fed to the input of the digital-to-analog converter 11, to the output of which is a stepped sinusoidal DTMF signal. The DTMF signal generator can be implemented on the basis of well-known technical means, described, for example, in: The use of integrated circuits in electronic computing. Handbook / Ed. B.N. Fayzulaeva, B.V. Tarabrina. - M .: Radio and communication, 1986. In this case, the converter 3 codes of DTMF signals into codes of division factors can be made, for example, in the form of a read-only memory chip 155PE 3 (p. 343), the implementation of the registers is described on p. 108, the implementation of the accumulators is described on p. 114.The inventive method and the DTMF signal generator are also implemented on the basis of the technical means of Microchip Inc. (8-bit single-chip microcontrollers like pic16f628), as part of the pulse-tone telephone dialer "Kadran - NKT - 01" manufactured by the company "Kadran" (Ukraine, Zaporozhye). Command system and internal organization microcontroller nodes are described in: Prokopenko B.Ya. Single-chip microcontrollers. Dodeka, 2000, ISBN8-87835-056-4. The description of the DTMF signal parameters is given, for example, in: Integrated Circuits: Microcircuits for telephony. Issue 1. - M .: Dodeka, 1994, 256 p. - ISBN-5-87835-003-3., P. 12, 13.

CLAIM

1. A method of generating two-tone frequency (DTMF) signals, including the selection of the first and second codes of sampling angles corresponding to the first and second frequencies of the DTMF signal components, cumulative summing separately of the first and second codes of sampling angles with respectively periodically fixed period corresponding to the sampling clock frequency, the first and the second results of the cumulative summation, obtaining the first and second discrete values of the DTMF signal components stored in the address located cells of the corresponding tables of discrete values of the DTMF signal components by reading from the corresponding tables at the addresses corresponding to the results of the cumulative summation of the sampling angle codes, summing the first and second discrete values of the DTMF signal components to obtain the third discrete value corresponding to the DTMF signal value, characterized in that the receipt of the first and second discrete values is their DTMF signal, stored in the address located cells of the corresponding tables of discrete values of the DTMF signal components, is performed by reading from the corresponding tables at the addresses corresponding to the results of cumulative summation, respectively, of the first and second sequences of integers, the averaged value of which corresponds to the codes of the sampling angles corresponding to the components of the DTMF signal .2. The method according to claim 1, characterized in that the average value of the sequence of integers forming the result of the cumulative summation is the arithmetic mean of these numbers. The method according to claim 1, characterized in that the periodic recording of the first and second accumulative summation results is performed with a period corresponding to the sampling clock frequency, which is different for different DTMF signals. A DTMF signal generator including a first accumulator adder, a first latching register, a first memory device, a second accumulator adder, a second latching register, a second memory device, a final adder, a digital-to-analog converter, and the output of the first accumulative adder is connected to the input of the first latching register, the output of the first latching register register is connected to the input of the first storage device, as well as to one of the inputs of the first storage adder, the output of the first storage device is connected to one of the inputs of the total adder, the output of the second storage adder is connected to the input of the second latching register, the output of the second latching register is connected to the input of the second storage device, as well as with one of the inputs of the second storage adder, the output of the second memory device is connected to another input of the total adder, the output of the total adder is connected to the input of the digital-to-analog converter for the output of which is the output of the DTMF signal generator, characterized in that the DTMF signal generator additionally contains a converter of DTMF signals in a sequence of integers, a divider of the master frequency of the DTMF signal generator with an adjustable division factor, a converter of DTMF signals into a division factor code, the first the output of the converter of DTMF signals in a sequence of integers is connected to another input of the first accumulator, the second output of the converter of codes of DTMF signals in a sequence of integers is connected to another input of the second accumulator, the output of the master frequency divider of the generator of DTMF signals with adjustable division ratio is connected to the clock input converter of DTMF signals codes in a sequence of integers, as well as with the clock input of the first latching register and the clock input of the second latching register, the output of the converter of DTMF signals codes into the coefficient code frequency divider is connected to the input for setting the division factor of the DTMF signal generator's master frequency, the input of the master frequency divider of the DTMF signal generator with an adjustable division ratio is the input of the master frequency of the DTMF signal generator, the input of the DTMF signal to the division factor code converter is connected to the input of the DTMF signal converter to sequence of integers and is the input of the DTMF signal generator. 5. The generator of DTMF signals according to claim 4, characterized in that the converter of codes of DTMF signals in a sequence of integers is made in the form of a controlled programmable memory, the memory of which consists of corresponding to the number of DTMF signals, memory areas consisting of cells corresponding to the length of the sequence of integers memory, made so that one half of the memory cell stores a number related to the first sequence of integers, and the other half of the memory cell stores a number corresponding to another sequence of integers that are the summands of the corresponding accumulators, and the programmable memory is controlled with the possibility of separate control over the selection of a memory area and a separate memory cell.

Tone dialing (Dual-tone multi-frequency signaling, DTMF) was developed by Bell Labs in the 50s of the last century for a revolutionary at that time push-button telephone... To represent and transmit digital data in a tone mode, a pair of frequencies (tones) of the speech frequency range... The system defines two groups of four frequencies, and the information is encoded by the simultaneous transmission of two frequencies - one from each group. This gives a total of sixteen combinations to represent sixteen different numbers, symbols and letters. DTMF coding is currently used in a wide variety of communications and control applications, as evidenced, for example, by International Telecommunication Union (ITU) Recommendation Q.23.

This article describes a DTMF tone generator circuit that reproduces all eight frequencies and produces a resulting two-tone output. The system in question was built on the basis of the Silego GreenPAK ™ SLG46620V chip and operational amplifiers Silego SLG88104V. The output signal is the sum of the two frequencies defined by the row and column of the telephone keypad.

The proposed circuit uses four inputs to select the generated frequency combination. The circuit also has an enable input that triggers oscillation and determines the length of time the signal is transmitted. The generator output frequency meets the requirements of the ITU standard for DTMF.

DTMF tones

The DTMF standard defines the encoding of the digits 0-9, the letters A, B, C and D and the symbols * and # as a combination of two frequencies. These frequencies are divided into two groups: a high frequency group and a low frequency group. Table 1 shows the frequencies, groups and corresponding symbol representations.

Table 1. DTMF tone encoding

	Treble group
Bass group

The frequencies were chosen to avoid multiple harmonics. Moreover, their sum or difference does not give another DTMF frequency. In this way, harmonics or modulation distortion are avoided.

Standard Q.23 specifies that the error of each transmitted frequency should be within ± 1.8% of the nominal value, and the total distortion (due to harmonics or modulation) should be 20 dB below the fundamental frequencies.

The resulting signal described above can be described as:

s (t) = Acos (2πfhight) + Acos (2πflowt),

where fhigh and flow are the corresponding frequencies from the high and low frequency groups.

Figure 1 shows the resulting signal for the digit "1". Figure 2 shows the frequency spectrum for a given signal.

Rice. 1. DTMF tone

Rice. 2. DTMF tone spectrum

The duration of DTMF tones can vary depending on the specific application that uses tone encoding. For the most common applications, duration values tend to lie between manual and automatic. Table 2 shows short description typical length of time for two types of dialing.

Table 2. Duration of signals with tone dialing

Set type	Treble group	Treble group
Set type
Hand set
Automatic dialing

For more flexibility, the DTMF generator offered in this manual is equipped with an enable input, which is used to start signal generation and determine its duration. In this case, the duration of the signal is equal to the duration of the pulse at the enable input.

Analog part of the DTMF generator circuit

ITU Recommendation Q.23 defines DTMF signals as analog signals created by two sine waves. In the proposed DTMF generator circuit, the Silego GreenPAK SLG46620V chip generates square wave signals with the desired DTMF frequencies. Analog filters and an adder are required to obtain sinusoidal signals of the required frequency and form the resulting signal (the sum of the two sinusoidal waves). For this reason, in this project, it was decided to use filters and an adder based on the SLG88104V operational amplifiers.

Figure 3 shows the structure of the proposed analog part of the device.

Rice. 3. Analog processing circuit for receiving a DTMF signal

Analog filters are used to produce sinusoidal signals from rectangular pulses. After filtering, the two signals are summed and the desired output two-tone DTMF signal is formed.

Figure 4 shows the result of the Fourier transform used to obtain the spectrum of a rectangular signal.

Rice. 4. The spectrum of the signal is rectangular

As you can see, the square wave contains only odd harmonics. If we represent such a signal with amplitude A in the form of a Fourier series, then it will have the following form:

Analysis of this expression allows us to conclude that if the analog filters have sufficient attenuation for harmonics, then it is quite possible to obtain sinusoidal signals with a frequency equal to the frequency of the original square wave.

Taking into account the interference tolerance specified in the Q.23 standard, it is necessary to ensure that all harmonics are attenuated by 20 dB or more. In addition, any frequency in the low frequency group must be combined with any frequency in the high frequency group. With these requirements in mind, two filters were developed, one for each group.

Low-pass Butterworth filters were used as both filters. The attenuation of a Butterworth filter of order n can be calculated as:

A (f) [dB] = 10 log (A (f) 2) = 10log (1+ (f / fc) 2n),

where fc is the cutoff frequency of the filter, n is the order of the filter.

The difference in attenuation between the lowest frequency and the highest frequency of each group can be no more than 3 dB, therefore:

A (fHIGHER) [dB] - A (fLOWER) [dB]> 3dB.

Given the absolute values:

A (fHIGHER) 2 / A (fLOWER) 2> 2.

In addition, as we said earlier, the harmonic attenuation must be 20 dB or more. In this case, the worst case will be the lowest frequency in the group, because its 3rd harmonic is the lowest frequency and is closest to the cutoff frequency of the filter. Considering that the 3rd harmonic is 3 times less than the fundamental, the filter must meet the condition (absolute values):

A (3fLOWER) 2 / A (fLOWER) 2> 10/3.

If these equations apply to both groups, then the filters used must be second order filters. This means that they will have two resistors and two capacitors if implemented using operational amplifiers. With third-order filters, the sensitivity to component tolerances would be lower. The selected cutoff frequencies of the filters are 977 Hz for the low-pass group and 1695 Hz for the high-pass group. With these values, the differences in signal levels in the frequency groups are consistent with the above requirements, and the sensitivity to changes in the cutoff frequency due to component tolerances is minimal.

The schematic diagrams of the filters implemented using the SLG88104V are shown in Figure 5. The ratings of the first R-C pairs selected in such a way as to limit the output current of the SLG46620V microcircuit. The second section of the filter determines the gain, which is 0.2. The amplitude of the square-wave signals sets the operating point of the op-amp to 2.5 V. The unwanted voltages are blocked by the capacitors of the output filters.

Rice. 5. Schematic diagrams of output filters

At the output, the signals of the filters are summed, and the resulting signal is the sum of harmonics selected from the group of low and high frequencies. To compensate for the attenuation of the filter, the amplitude of the output signal can be adjusted using two resistors R9 and R10. Figure 6 shows the adder circuit. Figure 7 shows the entire analog portion of the circuit.

Rice. 6. Schematic diagram adder

Rice. 7. Analog part of the circuit

Digital part of the DTMF tone generator circuit

The digital portion of the DTMF tone generator circuitry includes a variety of square wave generators, one for each DTMF frequency. Since eight counters are required to create these generators, the GreenPAK SLG46620V microcircuit was chosen for their implementation. At the exits digital circuit two rectangular signals are generated, one for each frequency group.

Square wave signals are generated by counters and D-flip-flops and have a duty cycle of 50%. For this reason, the switching frequency of the counters is twice the required DTMF frequency, and the DFF flip-flop divides the output signal by two.

The clock source for the counters is the built-in RC-generator 2 MHz, the frequency of which is additionally divisible by 4 or 12. The divider is selected taking into account the bit width and the maximum value of each counter required to obtain a specific frequency.

Fewer counts are required to generate high frequencies, so 8-bit counters are used to generate them, clocked from an internal RC oscillator, the signal of which is divided by 4. For the same reason, lower frequencies are implemented using 14-bit counters.

The SLG46620V has only three standard 14-bit counters, so one of the lower frequencies was implemented with an 8-bit CNT8 counter. In order for the number of samples to be within the range of 0 ... 255, to clock this CNT8, we had to use the signal of the RC generator divided by 12. For this circuit, the frequency with the largest number of samples was chosen, that is, the lowest frequency. This allowed us to minimize the error.

Table 3 shows the parameters of each square wave.

Table 3. Parameters of rectangular pulse generators

	Clocking	Frequency error [%]
Bass group



Treble group

As you can see from the table, all frequencies have an error of less than 1.8%, so they comply with the DTMF standard. These calculated characteristics, based on the ideal RC oscillator frequency, can be adjusted by measuring the RC oscillator output frequency.

Although in the proposed scheme all generators operate in parallel, but the signal of only one generator from each group will go to the output of the microcircuit. The choice of specific signals is up to the user. For this, four GPIO inputs (two bits for each group) are used with the truth table shown in Table 4.

Table 4. Bass group frequency selection table


Bass group

Table 5. Treble group frequency selection table


Treble group

Figure 8 shows the logic diagram of an 852 Hz square wave generator. This pattern is repeated for each frequency with appropriate counter settings and LUT configuration.

Rice. 8. Rectangular pulse generator

The counter generates an output frequency determined by its settings. This frequency is equal to twice the frequency of the corresponding DTMF tone. The meter configuration parameters are shown in Figure 9.

Rice. 9. Example of setting the counter of the generator of rectangular pulses

The counter output is connected to the clock input of the D-Flip Flop trigger. Since the DFF output is configured as inverted, if you connect the DFF output to its input, the D-flip-flop is converted to a T-flip-flop. The DFF configuration parameters can be seen in Figure 10.

Rice. 10. Example of setting the trigger of a square-wave generator

The signal from the DFF output goes to the input of the truth table LUT. LUT truth tables are used to select one signal for each specific R1-R0 combination. An example of a LUT configuration is shown in Figure 11. B this example if "1" is supplied to R1, and "0" is supplied to R0, the input signal is transmitted to the output. In other cases, the output is "0".

Rice. 11. Example of setting the truth table of a square-wave generator

As mentioned above, the proposed scheme has an Enable input. If a logical unit "1" is present at the Enable input, then the generated square-wave signals are fed to a pair of microcircuit outputs. The transmission duration is equal to the pulse width at the enable input. Several more LUT truth table blocks were required to implement this feature.

The high group uses one 4-bit LUT and one 2-bit LUT, as shown in Figure 12.

Rice. 12. Treble group output circuit

4-bit LUT1 is configured as an OR gate, so it outputs a logic high "1" if a "1" is present at any of its inputs. Truth tables C1 / C0 only allow selection of one of the oscillators, so the 4-bit LUT1 determines which signal is output. The output of this LUT connects to 2-bit LUT4, which only transmits a signal if a logic “1” is present at the enable input. Figures 13 and 14 show the configurations for 4-bit LUT1 and 2-bit LUT4.

Rice. 13. Configuration of 4-bit LUT1

Rice. 14.2-bit LUT4 configuration

Since there were no longer 4-bit LUT truth tables, two 3-bit LUTs were used for the low frequency group.

Rice. 15.Low frequency group output circuit

The complete internal diagram of the GreenPAK SLG46620V is shown in Figure 16. Figure 17 is the final schematic diagram of the DTMF generator.

Rice. 16. Block diagram of the DTMF tone generator

Rice. 17. Schematic diagram of the DTMF tone generator

Testing the DTMF Generator Circuit

At the first stage of testing the proposed DTMF generator, it was decided to check the frequencies of all generated square-wave signals using an oscilloscope. As an example, Figures 18 and 19 show square-wave outputs for frequencies of 852 Hz and 1477 Hz.

Rice. 18. Square wave signal 852 Hz

Rice. 19. Square wave signal 1477 Hz

Once the frequencies of all the square wave signals were verified, testing of the analog part of the circuit began. The output signals for all combinations from the low and high frequency group were examined. As an example, Figure 20 shows the sum of the 770 Hz and 1209 Hz signals, and Figure 21 shows the sum of the 941 Hz and 1633 Hz signals.

Rice. 20. DTMF tone 770 Hz and 1209 Hz

Rice. 21.DTMF tone 941 Hz and 1633 Hz

Conclusion

In this article, we proposed a DTMF tone generator circuit based on the Silego GreenPAK SLG46620V microcircuit and Silego SLG88104V operational amplifiers. The generator allows the user to select combinations of the required frequencies using four inputs and control the enable input, which determines the duration of the generation of the output signals.

Characteristics of the SLG46620V chip:

Type: programmable mixed signal microcircuit;
Analog blocks: 8-bit ADC, two DACs, six comparators, two filters, ION, four integrated oscillators;
Digital blocks: up to 18 I / O ports, connection matrix and combinatorial logic, programmable delay circuits, programmable function generator, six 8-bit counters, three 14-bit counters, three PWM generators / comparators;
Communication interface: SPI;
Supply voltage range: 1.8 ... 5 V;
Operating temperature range: -40 ... 85 ° C;
Housing version: 2 x 3 x 0.55 mm 20-pin STQFN.

Distinctive features:

Generating sinusoidal signals using pulse width modulation (PWM)
Combining various sinusoidal signals into one DTMF signal
Source codes in assembly language and C
Designed to work with STK500
Program code size 260 bytes / constant table size 128 bytes
Using the table conversion method

Introduction

This document describes a methodology for generating DTMF (Dual Tone Multi-Frequency) signals using any AVR microcontroller containing a Pulse Width Modulation (PWM) block and SRAM. These signals are widely used in telephony, where they are played when you press the dialing buttons of the telephone set. For the correct generation of the DTMF signal, two frequencies must be superimposed together: low frequency(fb) and high frequency (fa). Table 1 shows how different frequencies are mixed to produce DTMF tones when different keys are pressed.

Figure 1 - DTMF signal generator circuit

Table 1 - Tone shaping matrix

fb / fa	1209 Hz	1336 Hz	1477 Hz	1633 Hz
697 Hz	1	2	3	A
770 Hz	4	5	6	B
852 Hz	7	8	9	C
941 Hz	*	0	#	D

The rows of Table 1 show the low frequency values, and the columns - the high frequency values. For example, the matrix shows that when you press the "5" button, the frequencies fb = 770 Hz and fa = 1336 Hz should be mixed. As a result of the addition of two sinusoidal signals of different frequencies, a DTMF signal is formed

where the amplitude ratio K = A b / A a the original signals must meet the condition

Operating principle

In addition to general information The use of pulse width modulation will be shown below how pulse width modulation can generate sinusoidal signals. The next paragraph describes how using base frequency PWM get different frequencies. After considering the theoretical foundations, a description of the DTMF signal generator itself will be given. Generating sinusoidal signals

Depending on the ratio of the duration of the high VH and low VL voltage levels, the average value at the PWM output changes. If the ratio between the durations of both levels is kept constant, the result will be a constant voltage level VAV. Figure 2 shows a pulse width modulated signal.

Figure 2 - Level generation constant voltage

The voltage level is determined by the expression:

(3)

A sinusoidal signal can be generated provided that the average value of the voltage generated by the pulse width modulation changes every PWM period. The ratio between high and low levels should be set according to the voltage level of the sinusoidal signal at the appropriate time. Figure 3 illustrates this process. The initial data for PWM is calculated for each of its periods and written into the conversion table (TP).

Figure 3 also illustrates the relationship between the frequency of the main sine wave and the number of samples. The higher the number of samples (Nc), the higher the simulation accuracy of the resulting signal:

(4)

The PWM frequency depends on the PWM resolution. At 8-bit resolution, the end value (top of the count) of the timer is 0xFF (255). Because the timer counts up and down, this value must be doubled. Therefore, the PWM frequency can be calculated by dividing the clock frequency of the timer f CK by 510. Thus, with a timer clock rate of 8 MHz, the resulting PWM frequency is 15.6 kHz.

Figure 3 - Generation of a sinusoidal signal using PWM

Changing the frequency of a sinusoidal signal

Suppose that sinusoidal samples are read from the lookup table not sequentially, but one after another. In this case, at the same sampling rate, a signal with a doubled frequency will be generated (see Figure 4).

Figure 4 - Doubling the resulting frequency (XSW = 2)

By analogy, if you read not every second value, but every third, fourth, fifth (respectively, step width 3, 4, 5 ...), etc. can generate Nc frequencies in the range. Note that for high frequencies, the resulting waveform will not be sinusoidal. The width of the step according to the conversion table is denoted as X SW, where

(5)

The calculation of the current position in the TP for the next PWM period (when the timer overflows) is performed using the expression (6). New value in position X LUT depends on its previous state in position X "LUT with increment of step width X SW

(6)

Adding different frequencies to get a DTMF signal

DTMF signal can be generated using expressions (1) and (2). For simplicity of arithmetic operations, the value of the coefficient K is taken equal to 0.75 in order to replace the arithmetic operation with logical shifts. Taking into account expression (6), the current value for the PWM control can be calculated by the expression:

and taking into account that X LUTa=X "LUTa + X SWa ,X LUTb=X "LUTb + X SWb, we finally write

DTMF generator implementation

V this annex Consider building a DTMF tone generator using an 8-bit PWM output (OC1A) and a table with 128 samples of sinusoidal function values (Nc), each of which is set by 7 bits (n). The following expressions show this relationship and also show how to compute the elements of the lookup table:

(9)

The advantage of using 7 bits is that the sum of the high and low frequency values is one byte. For support complete set DTMF tones need to calculate 8 values for each DTMF frequency from Table 1 and enter them into the conversion table.

To achieve higher accuracy, the following solution is performed: values calculated by expression 5 require only 5 bytes. To use all 8 bytes, which will reduce the rounding error, this value is multiplied by 8. The pointer to the conversion table is written in the same way. But in this case, it takes two bytes to store the 8x value. This means that you need to perform 3 right-side shifts and a modulo operation in base Nc (logical multiplication by Nc-1) before using these bytes as a pointer to the sinusoid values in

Figure 5 - Diagram of the module for connecting to STK500

The PWM signal is generated at the OC1A pin (PD5). An additional output filter will help to better match the sine waveform. As the PWM frequency decreases, it may be necessary to apply a filter with a steeper frequency response in order to obtain a good result.

The keyboard connection is shown in Figure 1. The keyboard operation should be organized in such a way that it is possible to determine the pressed key. This can be done according to the following algorithm:

Determining the string of the pressed key
- configure the junior tetrad of port B to output and set the log. "0"
- configure the upper tetrad of port B to the input with the connection of pull-up resistors
- the line with the pressed button is defined as the category of the senior notebook with a log. "0"
Defining the column of the pressed key
- configure the senior nibble of port B to output and set the log. "0"
- configure the junior tetrad of port B to the input with the connection of pull-up resistors
- the column with the pressed button is defined as the category of the lowest nibble with a log. "0"

Note: In STK200, resistors are connected in series between PORTB pins and microcontroller pins BP5, PB6 and PB7 (see STK200 diagram). This will cause problems if the keyboard is connected to the PORTB connector.

Figure 6 illustrates the operation of the subroutine to determine the pressed key. The duration of the interval is determined depending on the key pressed. The interrupt routine uses this value to calculate the PWM settings for the two sine DTM tones. The interrupt handling procedure is shown in Figures 7 and 8.

This routine calculates a value to compare with the timer output for the next PWM period. The interrupt routine first calculates the position of the next fetch value in the lookup table and reads the value stored there.

The position of the sample in the lookup table is determined by the pulse width, and the actual pulse width is determined by the generated frequency.

The final value that is written to the timer compare register is determined using formula (7), which takes into account the sample values of both DTMF frequencies.

Figure 6 - Block diagram of the main program

Distinctive features

Generating sinusoidal signals using pulse width modulation (PWM)
Combining various sinusoidal signals into one DTMF signal
Assembler and C source codes
Designed to work with STK500
Program code size 260 bytes / constant table size 128 bytes
Using the table conversion method

Introduction

This document describes a methodology for generating DTMF (Dual Tone Multi-Frequency) signals using any AVR microcontroller containing a Pulse Width Modulation (PWM) block and SRAM. These signals are widely used in telephony, where they are played when you press the dialing buttons of the telephone set. To generate the DTMF signal correctly, two frequencies must be superimposed together: low frequency (fb) and high frequency (fa). Table 1 shows how different frequencies are mixed to produce DTMF tones when different keys are pressed.

Figure 1. DTMF signal generator circuit

Table 1. Tone shaping matrix

fb / fa	1209 Hz	1336 Hz	1477 Hz	1633 Hz
697 Hz	1	2	3	A
770 Hz	4	5	6	B
852 Hz	7	8	9	C
941 Hz	*	0	#	D

The rows of Table 1 show the low frequency values, and the columns show the high frequency values. For example, the matrix shows that when you press the "5" button, the frequencies fb = 770 Hz and fa = 1336 Hz should be mixed. As a result of the addition of two sinusoidal signals of different frequencies, a DTMF signal is formed

where the ratio of the amplitudes K = A b / A a of the original signals must meet the condition

Operating principle

In addition to general information about the use of pulse width modulation, it will be shown below how pulse width modulation can generate sinusoidal signals. The next paragraph describes how to obtain different frequencies using the PWM base frequency. After considering the theoretical foundations, a description of the DTMF signal generator itself will be given. Generating sinusoidal signals

Figure 2. Generation of constant voltage level

The voltage level is determined by the expression:

(3)

(4)

Figure 3. Generating a sinusoidal signal using PWM

Changing the frequency of a sinusoidal signal

Figure 4. Doubling the resulting frequency (XSW = 2)

By analogy, if you read not every second value, but every third, fourth, fifth (respectively, step width 3, 4, 5 ...), etc. can generate Nc frequencies in the range. Note that for high frequencies, the resulting waveform will not be sinusoidal. The step width according to the conversion table is denoted as X SW, where

(5)

The calculation of the current position in the TP for the next PWM period (when the timer overflows) is performed using the expression (6). The new value at the X LUT position depends on its previous state at the X "LUT position with the addition of the X SW step width

(6)

Adding different frequencies to get a DTMF signal

and taking into account that X LUTa = X "LUTa + X SWa, X LUTb = X" LUTb + X SWb, we finally write

DTMF Generator Implementation

This appendix shows how to build a DTMF tone generator using an 8-bit PWM output (OC1A) and a 128-sample sine function (Nc) sample table, each specified by 7 bits (n). The following expressions show this relationship and also show how to compute the elements of the lookup table:

(9)

The advantage of using 7 bits is that the sum of the high and low frequency values is one byte. To support a full set of DTMF tones, it is necessary to calculate 8 values for each DTMF frequency from Table 1 and enter them into the conversion table.

To achieve higher accuracy, the following solution is performed: values calculated by expression 5 require only 5 bytes. To use all 8 bytes, which will reduce the rounding error, this value is multiplied by 8. The pointer to the conversion table is written in the same way. But in this case, it takes two bytes to store the 8x value. This means that you need to perform 3 right-side shifts and a modulo operation in the base Nc (logical multiplication by Nc-1) before using these bytes as a pointer to the values of the sinusoid in

Figure 5. Diagram of the module for connecting to STK500

Determining the string of the pressed key
- configure the junior tetrad of port B to output and set the log. "0"
- configure the senior tetrad of port B to the input with the connection of pull-up resistors
- the line with the pressed button is defined as the category of the senior notebook with a log. "0"
Defining the column of the pressed key
- configure the senior nibble of port B to output and set the log. "0"
- configure the junior tetrad of port B to the input with the connection of pull-up resistors
- the column with the pressed button is defined as the category of the lowest note with a log. "0"

The position of the sample in the lookup table is determined by the pulse width, and the actual pulse width is determined by the generated frequency.

The final value that is written to the timer compare register is determined using formula (7), where the sample values of both DTMF frequencies are taken into account.

Figure 6. Block diagram of the main program

Figure 7. Block diagram of the timer overflow interrupt handling routine

Figure 8. Block diagram of the "GetSample" sample reading procedure

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