Digital signal processor signals (Digital Signal Processor - DSP) is a specialized programmable microprocessor designed to manipulate the real-time digital data stream. DSP processors are widely used to handle graphics information, audio and video signals.

Any modern computer Equipped with a central processor and only a few - digital signal processing processor (DSP - Digital Signal Processor). The central processor, obviously, is a digital system and processes digital data, so at first glance it is unclear the difference between digital data and digital signals, that is, those signals that handle the DSP processor processes.

Digital signals, in general, naturally attribute all digital information streams that are formed during telecommunications. The main thing that distinguishes this information is not necessarily entered into memory (and therefore it may be inaccessible in the future), therefore, it is necessary to process it in real time.

The number of digital information sources is almost unlimited. For example, downloaded files in MP3 format contain digital signals, actually representing sound recording. In some camcoders, video signals are digitized and recorded in digital format. In expensive models of wireless and cell phones, voice is also converted to a digital signal.

Variations on the topic

DSP processors are fundamentally different from microprocessors forming the desktop of the desktop. By the nature of its activities, the central processor has to perform unifying functions. It must manage the work of various computer hardware components, such as drives, graphic displays and a network interface in order to ensure their consistent work.

This means that the central processors of desktop computers have a complex architecture, because they must support such basic functions as memory protection, integer arithmetic, floating point operation and vector graphics processing.

As a result, a typical modern central processor supports several hundred teams that ensure the execution of all these functions. Therefore, we need a module for decoding commands, which would allow to implement a complex dictionary of commands, as well as many integrated schemes. They, in fact, must perform actions defined by the teams. In other words, a typical processor in the desktop contains tens of millions of transistors.

DSP processor, on the contrary, should be a "narrow specialist". Its only task is to change the flow of digital signals, and do it quickly. The DSP processor consists mainly of high-speed hardware circuits performing arithmetic functions and manipulating bits optimized in order to quickly change large amounts of data.

Because of this, the set of commands from DSP is much less than that central processor desktop computer; Their number does not exceed 80. This means that the DSP requires a lightweight team decoder and a much smaller number of executive devices. In addition, all executive devices ultimately must support high-performance arithmetic operations. Thus, a typical DSP processor consists of no more than several hundred thousand transistors.

As a highly specialized, the DSP processor copes perfectly with its work. His mathematical functions allow you to continuously receive and change the digital signal (such as recording to MP3 or recording a call on a cell phone), without braking the transmission of information and without losing it. For increase bandwidth The DSP processor is equipped with additional internal data tires that provide faster data transfer between arithmetic modules and processor interfaces.

Why do you need DSP processors?

The specific features of the DSP processor in terms of information processing make it an ideal tool for many applications. Using algorithms based on the appropriate mathematical apparatus, the DSP processor can perceive the digital signal and perform convolution operations to gain or suppress those or other signal properties.

Due to the fact that in DSP processors, significantly less transistors than in central processors, they consume less energy, which allows them to be used in battery products. Their production is extremely simplified, so they find themselves use in low-cost devices. The combination of low power consumption and low cost determines the use of DSP processors in cell phones And in robots-toys.

However, the spectrum of their application is far from being limited. By virtue of a large number of arithmetic modules, the presence of data integrated on the memory crystal and additional data tires can be used to support multiprocessing processing. They can compress / unpacking the "live video" when transmitting on the Internet. Similar high-performance DSP processors are often used in equipment for organizing video conferencing.

Inside DSP.

The diagram below illustrates the structure of the Motorola DSP 5680X processor core. Separate internal tires of commands, data and addresses contribute to a sharp increase in the bandwidth of the computing system. The presence of the secondary data bus allows the arithmetic device to read the two values, multiply them and perform the operation of accumulating the result for one processor clock.

Inadvertently stumbled upon video from "Chip and Dip" # 1 Digital sound processing ADAU1701 | Open project | Start
And then "covered" with all sorts of memories about this topic. I decided to check what was going on in our time on this front, found that a lot of good and interesting.

The quality of processing has grown significantly, the price has fallen significantly and sound DSP (Digital Signal Processing) is already knocking on our house! :)
In this video, the Sigmadsp Adau1701 chip is considered and I decided to see what you can create with him and was very impressed with the possibilities.
In Russian, you can read about them (). For me, this DSP allows you to build a normal acoustic system with an external crossover. The possibilities of the system is unimaginably more than my sweat. It allows you to program yourself a complete newcomer in programming, but understanding the sound components and how they work: filters; crossovers; Equalizers, etc. etc. This knowledge is needed to configure all this.
This is the example of a project example in the program of service and programming DSP:

As you can see almost no "digital values", and everything calls for "sound".
Of course, his ADC and DAC "is far from Hi-End, but the average Hi-Fi, but for the home of this quality is enough, and the possibilities are very high. It is very good that the DSP has a double calculation accuracy (56-bit) and it is set by default. .
Well ... Small / incomplete diffirable sang, now reality.

There are fees in different versions:
Option 1. Complete test fee from the manufacturer costs ~ 12-15 thousand rubles And allows you to avoid anything. IMHO the greatest advantage over the rest is a complete SPDIF, i.e. and digital input and digital output Results. Also allows you to debug algorithms "on the fly". Order "for the hill" from the manufacturer's website.
Option 2.. This is a slightly chopped layout from the workshop - a set of BM2114DSP. He has all the inputs / outputs analog, but debugging is still "on the fly."
Cost 4900 rubles.
Option 3.. This is the maximum simplified version of the use of DSP from "Chip and Dip" of their Labotoria "Electronic Forces".
The kit is called Digital Signal Processors RDC2-0027V1, a digital sound processing module on Sigmadsp ADAU1701, SIGMASTUDIO
This is a variant with the lack of programming "on the fly". Create a binary, convert and "pour" with the "whistle" in the errom board. Takes it a little time, but takes away, and requires an understanding of the process. :)
Cost of payment 950 Rubles.

Yes, I will clarify, the fee after programming works as an independent device !!! Those. PC is always not needed! And to the board you can connect the "twist" (encoders); buttons, etc., i.e. external methods Adjustments are sufficient, not necessarily to go into the DSP code.
The choice is yours...

Now concerned my wishlist from the past. One of the big problems of passive filters is phase distortions and the greater the steepness of the filter downturn, the greater the phase distortion. Because of them, there are many pride in which it is extremely difficult to get rid of and difficult to coordinate different frequency bands.
Data Digital Filters do not suffer from this and allow you to make a lot to match the cutting strips. But it becomes necessary to use instead of one amplifier - three, one for each frequency range (once the 3-way column, then the bands 3 and amplifiers are obtained 3). Of course, they can be optimized by power (for example, in my case there will be a LC - 30W; SC - 20W; HF - 10W), but here on the possibilities and an amateur, I think the unification will win. :)

At the end set video

Example how to combine the "digit"

The guy collects a monster on two DSP

Not so long ago, thanks to great progress in the field of sound processing and computer technologies, such a concept as DSP - Digital Signal Processing (digital signal processing) has been firmly included in our consciousness. Digital signal processing is a field of technology engaged in real-time computing algorithms. DSP tells us about the possibility of this or that transceiver to implement this service through its technical capabilities. Some modern transceivers have digital processing both reception and transmission. It is safe to say that digital processing provides quality that matches new technologies and the time we live in.

Digital processing in relation to radio amateur is most often used in the processing of the signal from the ether, in order to ensure better reception, eliminate interference accompanying the transfer of the correspondent. This is done when working with any kind of communication, including digital. For this purpose, a computer with a built-in sound card (ZK) and the corresponding software can often use. However, in real time, the signal is processed with a delay, and if in the reception mode it is still tolerant, then during transmission - no.

Working SSB and using computer hardware and software capabilities in the signal processing from the microphone, which is connected to the sound card of the computer (followed by the feed signal to the transceiver balanced modulator), the delay is very significant. We are talking It is not easy to enhance the signal from the microphone to a certain level with the help of the CC, and on the use of special signal processing programs in real-time. The situation is even more aggravated when working with such digital species as AMTOR, PACTOR, PACKET, when the computer is simultaneously used, say, as a notch filter and, together with the TNC controller available at the TNC station, it provides listed types of work. Delay in signal processing in the computer in such cases is invalid. In order to get rid of this problem, use Audigy-2 audio card (for example, Audigy-2 24 Bit 96 KHz).

Also, this sound card has a hardware embedded effects processor, which allows using software and hardware capabilities, to process the signal in real time at a sufficiently high level, i.e. In transmission mode, for example, in telephone types of work - SSB, AM, FM - have a good equalizer, compressor, limiter, and in reception mode - notch filter, expander or something else.

All this is possible even with personal computer from pentium processor 200 ... 500 MHz, although the use of more powerful machines is welcomed, since there are even greater features of signal processing using software - Plug In and appropriate programs, the processing algorithm that requires higher computer performance.

In this case, modern technologies allow not to use external expensive digital processing devices, but to some extent to imitate their operation using for this computing power Computer central processor and sound card. However, it is possible with really very high computer resources. Using these technologies, it remains only to install the docking node - the interface - between the transceiver and the computer and successfully use the possibility of the latter.

Paying for proper digital signal processing in the transceiver or using a computer, radio amateurs also use external DSP processing units. This is a relatively new direction in amateurs.

It is about digital processing of the signal using high-tech, modern equipment used in broadcasting and musical studios, providing absolutely professional quality and naturalness of sound. These are high-quality mixer consoles, as well as all sorts of analog-digital multi-band (more often parametric) equalizers, noise cancellation systems - Noise Gate, compressors, limiter, multi-effect processors, allowing different sound processing algorithms.

It should be noted that DSP is general concept. You can have a DSP equalizer, compressor, other devices and even a microphone preamp. Having a DSP function in transceiver is one, have a whole DSP equipment studio - these are completely different features. This is true if in both cases the mentioned processing is carried out at low frequency.

Famous manufacturers of DSP equipment - Behringer www.behringer.com, Alesis www.alesis.com and others - have a huge list of it, and much of it can successfully be applied by radio amateurs.

Each of these devices performs its task and, as a rule, contains precision 24-bit ADCs and DACs (analog-to-digital and digital-analog converters) in its two channels (analog-digital and digital-analog converters), operating on the professional frequency of discredit and having a range of operating frequencies of 20 Hz ... 20 kHz .

Brief certificate

Analog-digital and digital-analog converters. The first converts an analog signal into the amplitude digital value, the second performs the reverse transformation.

The principle of operation of the ADC consists in measuring the level of the input signal and issuing the result in digital form. As a result of the work of the ADC, the continuous analog signal turns into a pulse, while simultaneously measuring the amplitude of each pulse. The DAC receives a digital amplitude value at the input and outputs the voltage pulses or current of the desired value, which the integrator located behind it (analog filter) turns into a continuous analog signal.

As any new (particularly demanding investment of money), it has its supporters and opponents. To achieve a high level of quality, use is required to transmit a wider filter in the transceiver SSB-3 kHz, and not 2.4 kHz or 2.5 kHz, but this does not go beyond the regulations of the amateur radio communications in terms of the equipment used.

Today, reject the right to the existence of the direction in the processing of sound with the help of additional devices can only be lazy, envious or one who does not welcome progress and new technologies.

Hi-Fi Audio In SSB is the high quality of the NF signal processing in SSB, or "Extended SSB" - extended SSB - phrases, often audible and partially explaining the more than 10-year activity of radio amateurs from around the world at a frequency of 14178 kHz.

Here is the "round table" of lovers of studio signals and ways to receive them. This is a round table, which does not have time. Work is carried out almost clouds. In the world there are a little more than 100 active radio amateurs using these technologies are not very disturbed by QRM, they have already achieved significant success in equipping their stations and have not only high-end transceivers power amplifiers (often High Power class), but also the most important Effective directional antennas

Many are heard at almost any passage, and sometimes in its absence of Bill, W2ONV, from New Jersey - the oldest radio amateur and a large specialist in the field of sound processing using external DSP devices having a power of 1.5 kW (maximum allowed in the USA) and Two sfazed four-element wave canals, it has been almost always heard in Europe for many years at a frequency of 14178 kHz. People working on this "round table" - different ages, mostly from 30 to 80 years old, and the tone in working to a greater extent Specify radio amateurs of the older age group and this is not a tribute to the older generation, this is a statement of the fact that they have great success in the field of digital processing, because they own sufficient knowledge and more serious equipment.

Radio amateurs on "14178" - weathered and calm, fully enthusiastic ones who are always happy with their own business and provide them with all of the assistance of a great contribution to the development of sound processing themselves, the same radio amateurs, placing useful information on their Web pages on the Internet, many will agree that John, NU9N, created a website on the Internet, made a huge contribution to the development of this area (www.nu9n.com), where he posted a practical textbook on the use of external digital processing devices, the sequence of their connection (very important question) setting parameters on the NU9N website can also be Download samples of DSP signals of many radio amateurs to listen to them quite interesting.

Unfortunately, in the quantitative plan of the station from the former union, 14178 kHz is very weak - Vasily, ER4DX, Igor, EW1mm, Sergey, EW1DM, Sergey, RW3PS, Victor, RA9FIF and Oleg, RV3AAJ (no other data) affects the lack of extra finances the acquisition of audio equipment, as well as the mentality of people - when there is no time and money to do to all this, it means that it is bad, it means that it is not necessary to obviously, it should be focused on the fact that all directions in amateurs have the right to life, be it competitions, QRP (or QRO), DX'ing, and even the absence of some knowledge of Morse, a foreign language, and much more - this is also a "direction", and we, alas, to this already seem to be used to get used to it.

We wish the "young '(10 years for the radio - a term of small) success in their hard hobby, and all who have already achieved results in other areas, I invite you to join the community of studio signals, in the end, there is nothing more interesting to the debut.

This article opens a series of publications dedicated to multi-core digital TMS320C6678 signaling processors. The article gives general view about the processor architecture. The article reflects the lecture-practical material offered by listeners in the framework of advanced training courses on the "Multi-core processors of digital signal processing of C66X signals by Texas Instruments" conducted in Ryazan State Radio Engineering University.

The TMS320C66xX digital signal processors are built by the Keystone architecture and are high-performance multi-core signal processors, working with both fixed and floating point. The Keystone architecture is a principle of manufacturing multi-core systems on a crystal, which allows you to organize the effective joint operation of a large number of DSP and RISC-type kernels, accelerators and peripherals, with sufficient bandwidth of the internal and external data transfer channels, the basis of the hardware Components: Multicore Navigator (Internal Interface Data Exchange Controller), Teranet (Internal Data Transfer Bus), Multicore Shared Memory Controller (Access Controller) and Hyperlink (Interface with external devices on intracralic speed).

The architecture of the TMS320C6678 processor, the most high-performance processor in the TMS320C66XX family, is shown in Figure 1. The architecture can be divided into the following main components:

• set of operating cores (CorePack);
• subsystem of work with general internal and external memory (Memory Subsystem);
• peripherals;
• network coprocessor (Network Coprocessor);
• internal forwarding controller (Multicore Navigator);
• service hardware modules and internal tire Teranet.

Picture 1. Total TMS320C6678 processor architecture

The TMS320C6678 processor operates on a clock frequency of 1.25 GHz. The operation of the processor is based on a set of C66x CorePack operating cores, the number and composition of which depend on the specific model of the processor. CSP TMS320C6678 includes 8 DSP-type cores. The kernel is a basic computing element and includes computing blocks, register sets, software, software, and data memory. The memory included in the kernel is called local.

In addition to local memory, there is a general memory for all cores - the general memory of the multi-core processor (MSM multicore Shared Memory). Access to the shared memory is carried out through the memory management subsystem (Memory Subsystem), which also includes an EMIF external memory interface for exchanging data between the processor and external memory chips.

The network coprocessor increases the efficiency of the processor in the composition of various types of telecommunication devices, implementing hardware-type for this sphere of data processing task. The operation of the coprocessor is based on the packet acceptance of the packet data (Packet Accelerator) and the Security ACCEELERATOR. The processor specification lists the set of protocols and standards supported by these accelerators.

Peripheral devices include:

• Serial Rapidio (SRIO) version 2.1 - provides the data transfer rate to 5 GBAUD per line with the number of lines (channels) - to 4;
• PCI Express (PCIE) Gen2 versions - provides the data transfer rate to 5 GBAUD per line with the number of lines (channels) - to 2;
• Hyperlink. - the interface of the inner tire that allows switching processors built by the Keystone architecture directly with each other and exchange for intrarality; data transfer rate - up to 50 GBAUD;
• Gigabit Ethernet (GBE) Provides transfer rates: 10/100/1000 Mbps and is supported by a hardware accelerator network communications (network coprocessor);
• EMIF DDR3. - interface of external memory type DDR3; It has a bit of 64 bits bus, providing addressable memory space up to 8 GB;
• Emif. - the interface of the external memory of general purpose; It has a tire bit 16 bits and can be used to connect 256MB Nand Flash or 16MB NOR Flash;
• TSIP (Telecom Serial Ports) - telecommunication serial port; Provides transfer rates to 8 Mbps per line with the number of lines - to 8;
• UART. - universal asynchronous serial port;
• I2c. - internal communication tire;
• Gpio. - general purpose input - 16 conclusions;
• SPI - universal serial interface;
• Timers (Timers) - Used to generate periodic events.

Service hardware modules include:

• debug and Trace Module (Debug and Trace) - allows you to receive debugging tools access to the internal resources of the working processor;
• boot ROM (Boot ROM) - stores the initial loading program;
• hardware Semaphore - serves for hardware support for organizing sharing parallel processes to common resources processor;
• power Management Module - implements the dynamic control of the power modes of the processor components in order to minimize energy consumption at the moments when the processor does not work in full power;
• fAPC scheme - forms internal clock frequencies processor from an external reference tacting signal;
• direct Memory Direct Access Controller (EDMA) - Manages the data transfer process, unloading the CSP operating cores and being an alternative to Multicore Navigator.

The internal forwarding controller (Multicore Navigator) is a powerful and efficient hardware module responsible for data arbitration between different processor components. Multi-core systems on the TMS320C66XX crystal are very complex devices and to organize the exchange of information between all components of such a device, a special hardware block is required. Multicore Navigator allows nuclei, peripheral devices, host devices do not assume the functions of controlling the exchange of data. When a processor component needs to send an array of data to another component, it simply indicates the controller, which and where to transfer. All functions for the shipment itself and the synchronization of the sender and the recipient takes the Multicore Navigator.

The basis of the functioning of the multi-core processor TMS320C66xX from the position of high-speed data exchange between all numerous processor components, as well as external modules, is the internal tire of Teranet.

In the next article, the architecture of the C66X operating core will be discussed in detail.

1. Multicore Programming Guide / SPRAB27B - August 2012;
2. TMS320C6678 MULTICOR FIXED AND FLOATING-POINT DIGITAL SIGNAL PROSESSOR DATA MANUAL / SPRS691C - FEBRUARY 2012.

Digital DSP Signal Processor (Digital Signal Processor)

FeaturesDSP.

DSP are specialized processors for applications requiring intensive computing.
If you closer to consider, for example, the process of multiplying two numbers while maintaining the result in traditional microprocessors, you can see how the machine time is consumed: first the command sampling occurs (the command address is set to the address bus), then the first operand (the operand address is set to the address bus. ), then the operand is transferred to the battery, then there is a sample of the second operand, etc. The acceleration of this process in the general purpose processor is impossible due to the presence of the only address bus and the only data bus, as well as a single data bank. In view of this, all operations to extract operands from memory, command samples and save the operand are performed sequentially using the same data bus and address bus. In addition, if you consider the operation of the cyclic summation of the arithmetic series, you can see that there is no time that there is no time for the memory of the first cycle command, with checking the cycle conditions (meter) and return to the first team. Also, large unproductive costs exist when transition to a subroutine and return (recording and restoring register values \u200b\u200bfrom stack) and with many other operations. If you consider great amount Mathematical operations when performing digital signal processing, it becomes clear that very sensitive losses are inevitable in accuracy of calculating when rounding, which cannot but affect the total result. This occurs due to the same bit of all general-purpose processors registers.
With digital signal processing, all these costs are not allowed. In order to overcome this shortage of general-purpose processors and digital signals were developed (DSP - Digital Signal Processor).

Thirty Harvard architecture

Its feature consists primarily in the fact that, unlike the two tires familiar to us: the tires of the address and data bus, as well as one memory bank, the DSP has at least 6-7 different tires and 2-3 memory bank. This feature is intended to maximize the execution of multiplication operation with the preservation of the result, which is undoubtedly the most consumed and resource-intensive in digital processing of signals. DSP architecture allows for one machine cycle produce:

• selection of the command via the bus address bus and program bus tires;
• selection of two operands for multiplication operation via two data address bus;
• enhancing operands into batteries through two data tires;
• multiplication operation;
• save the result in the battery.

Thus, the trial Harvard architecture allows you to perform almost any operation for one machine cycle.
As an example of the efficiency of DSP use when implementing digital signal processing algorithms, you can bring the following fact: the completion time of the complex 1024-point Fourier transform is 20 ms for 486DX2 66 MHz (32-bit) and 3.23 MC for 24-bit 33 MHz DSP56001 Motorola or Motorola 3.1 MS for 32-bit 33 MHz DSP TMS320C30 with Floating Arithmetic TEXAS INSTRUMENTS.
However, as already mentioned, digital signal processors have honors not only high performance measured in the speed of multiplication / accumulation operations (MIPS - millions of teams per second), but also characteristics such as a sequence of program execution, arithmetic operations and memory addressing, Allowing to reduce unproductive time spending to a minimum. In general, the DSP differs from other types of microprocessors and microcontrollers in the following five main features:

• Fast arithmetic.

DSP - The processor must perform the execution of multiplication operations, multiplication with accumulation, cyclic shift, as well as standard arithmetic and logical operations.

• Advanced dynamic volume for multiplication / accumulation operation.

The calculation operation of a certain sequence of values \u200b\u200bis fundamental for algorithms implemented on DSP. Overflow protection is necessary to avoid data loss.

• Selection of two operands for one cycle.

Obviously, for most operations performed by DSP, two operands are needed. Thus, to achieve maximum performance, the processor must be able to produce a simultaneous sample of two operands, which also requires the presence of a flexible addressing system.

• The presence of hardware cyclic buffers (embedded and external).

The wide class of algorithms implemented on DSP requires the use of cyclic buffers. Hardware support for the cyclic return of the address pointer or modular addressing reduces the non-production costs of processor time and simplifies the implementation of algorithms.

• Organization of cycles and branches without loss in performance.

DSP algorithms include a lot of repetitive operations that can be implemented in the form of cycles. The possibility of organizing the sequence of execution of the code program in the cycle without performance loss is distinguished by DSP from other processors. Similarly, time loss when performing a branch operation by condition is also unacceptable when digital processing of signals.
However, it should not, however, think that DSP can completely replace general-purpose processors. As a rule, digital signals processors have a simplified system of commands that do not allow performing operations that are not related to mathematical calculations with the same efficiency as general purpose processors. Attempting to combine in one processor power in mathematical calculations and flexibility in operations of another kind leads to an unjustified increase in cost. Therefore, DSPs are used more often in the form of coprocessors (mathematical, graphic, accelerators, etc.) with the main processor or as an independent processor, if this is sufficient.

DSP.firmsMotorola.

Motorola is currently producing three families of digital signal processors. This is the DSP56100, DSP56000 and DSP96000 series. All microcircuits of the series are based on the DSP56000 architecture and differ in the bit (16, 24, 32 bits, respectively) and some built-in devices. Thus, the compatibility of the microcircuits of all three families is reached. All DSP firms Motorola are built according to the identical trial Harvard architecture described earlier with a large number component parts, ports, controllers, memory banks and tires working in parallel in order to achieve maximum speed.
Data transfer It occurs on bidirectional data tires (one for DSP56100 (XDB) and two for DSP56000 and DSP96000 (XDB and YDB)), program data bus (PDB) and a common data bus (GDB). In addition, DSP96000 has a separate direct access bus (DDB). Transmission of data between the tires occurs through the internal Tire management device.
Addressing It is carried out on two unidirectional tires: the data address bus and program address bus.
Bita manipulation unit Allows you to flexibly manage the state of any bit in registers and memory cells. The presence of such an opportunity is an advantage in relation to DSP other users.
Arithmetic and logical device (Allu) performs all arithmetic and logical operations and has in its composition input registers, batteries, battery expansion registers (8-bit, allowing 256 overflows without loss of accuracy), parallel one-bit multiplication block with preservation (MA), as well as shift registers. Flexible command system allows you to perform Alu per one Cycle of multiplication command, multiplication with the preservation of the result, summation, subtraction, shift and logical operations. The characteristic feature of the DSP of the company Motorola is the ability to double the input registers of Allu and an increase in this way of the discharge of the processed numbers. Another important feature is the presence of a division operation, often absent from other manufacturers and a replaceable multiplication operation for a reverse number, which leads to loss of accuracy.
Address formation unit Performs all calculations related to the definition of addresses in memory. This unit works independently of the other processor blocks. For one cycle, two read operations can be performed from the memory or one recording operation. Motorola's DSP has an extremely powerful powerful addressing system that allows you to produce almost any manipulation with data for one command. This important feature is beneficial to DSP, manufactured by the company, from analogs. The module addressing is convenient for the organization of ring buffers without checking out the border, which makes it possible to avoid unproductive time. The possibility of addressing inversion of significant bits facilitates the implementation of the BPF.
Block Office Execution program Contains 6 registers, among which Pointer address cycle and Counter cyclesallowing you to organize hardware support for the organization of cycles in the DSP company Motorola, at which additional machine cycles are not spent on checking the exit conditions from the cycle and change the cycle counter. A number of repetitions are clearly indicated in the DO cycle organization command.
The system stack is a separate part of the 15 words of RAM, and can store information about 15 interrupts, 7 cycles or 15 outputs into the subroutine. Data from the stack is read in one cycle, thus reducing the non-production costs of the processor time.
Motorola's main distinguishing feature of DSP is the presence of all microcircuits Intrachrystal emulatorallowing you to debug programs without the use of additional hardware. Therefore, there is no need to buy expensive debugging agents. The emulator allows you to record / read registers and memory cells, setting the stoppoints, step-by-step program execution and other actions by submitting commands to a 4-wired bus.
To reduce energy consumption at the moments when the calculations are not performed, two modes with reduced energy consumption are provided: Stop.and Wait.
To work, together with other processors and direct memory channels, a built-in memory is provided. HOST interface.
Possessing all the above properties necessary for digital signal processing, Motorola's DSP has an extremely powerful and flexible command system that allows the user to work conveniently and efficiently working with processors.

DSP96000 family

The DSP96000 family has a 32-bit architecture and supports floating point operations. Family microcircuits are designed for computer Systems Multimedia. The DSP of this series can also work as independent chips, and through two independent 32-bit ports can consistently exchange data with other processors.
The family microcircuits are in their composition 6 memory banks, 8 tires and 4 autonomous computing units: Allu, a program control unit, a double address generation unit and a built-in dual-channel direct access controller.
Characteristics of the DSP96000 microcircuit:

• 49.5 MIPS at 40 MHz
• 60 MFLOPS at 40 MHz, cycle 50 ns
• 32-bit organization
• 2 bank memory bank 512x32 bits
• 2 data memory bank 512x32 bits
• RAM programs 1024x32 bits
• booting ROM volume 56 bytes
• addressable external memory 2x232 32-bit words of data memory and programs
• built-in emulator
• 2 channels of direct memory access
• 2 Channel exchange with external processors
• case with 223 conclusions in the PGA or QFP housing

DSP.firmsTexas.Instruments

The DSP of this company is represented by the following microprocessors: TMS 32010, TMS 320C20, TMS 320C25, TMS 320C30, TMS 320C40, TMS 320C50.

Features of architecture TMS320C25.

The TMS320C2X architecture is based on the architecture of the TMS32010 - the first member of the DSP microprocessor family. In addition, the set of his commands overlaps the set of microprocessor commands TMS32010, which saves software compatibility down up.
The TMS320C2X microprocessor has one battery and uses the Harvard architecture in which data memory and memory programs are separated into different address spaces. This allows you to completely overlap the call and execution of the command. The system of commands includes data exchange commands between two memory regions. Outside the microprocessor of the data memory space and programs are combined into the same bus in order to maximize the range of addresses in both areas of memory and at the same time maximize the amount of output contacts. Inside the microprocessor, the space and data space is displayed on different tires to increase the power of the processor and the speed of program execution.
Increased system design flexibility is provided by the crystal by two large RAM memory blocks, one of which can be used both as a memory memory and as data memory. Most processor commands are performed in one machine cycle using both the external memory of the quick sample programs and use. internal memory RAM. The flexibility of the TMS320C2X microprocessor provides also connecting slow external memory or peripheral devices using the READY signal; But in this case, the commands are performed for several cycles.

Memory organization

On the TMS32020 crystal there is 544 16-bit words of the RAM memory, of which 288 words (blocks B1 and B2) are always assigned to the data, and 256 words (block B0) in different configurations of the processor can be used either as data memory or as a program memory. TMS320C25 In addition, it is provided with a disguised ROM (ROM), a volume of 4K words, and the TMS320E25 - the memory of 4k words with ultraviolet erasing EPROM.
TMS320C2X is provided by three separated address spaces - for the memory of programs, for data memory and for I / O devices, as shown in Fig. 6.5. These spaces outside the crystal differ using -ps, -ds, -is signals (for program spaces, data, input / output, respectively). The memory blocks B0, B1, B2 located on the crystal are covered in the amount of 544 memory words with arbitrary access (RAM). RAM B0 (256 words) is located on 4 and 5 pages of data memory, if it is assigned to the data, or by addresses\u003e FF00 -\u003e FFFF, if it is part of the program memory. Block B1 (data only) is located on 6 and 7 pages, and the B2 block occupies the older 32 words 0 pages. Note that the remaining part of the page is occupied by 6 addressable registers and the backup area; 1 - 3 pages are also a backup area. Backup areas cannot be used to store information, when reading their contents are not defined.
Internal program memory (ROM), located on a processor crystal can be used as a junior 4K word memory words. To do this, the MP / * MC contact must be served a low-level signal. To prohibit the use of the internal ROM field on MP / * MC, you must submit a high level.

External memory and I / O interface

The microprocessor TMS32020 supports wide range Interface systems. The address space of data, programs and I / O provides memory conjugation and external devices, which increases the capabilities of the system. Local memory interface consists of:

• 16-bit data tire (D0-D15);
• 16-bit address tire (A0-A15);
• address spaces, programs and input / output selected by signals (* DS, * PS and * IS);
• different system management signals.

R / * W signal controls the direction of transmission, and the * STRB signal controls the transmission.
I / O space contains 16 ports for inputs and 16 ports for output. These ports provide a complete 16-bit interface with external data bus devices. Disposable input / output using In and Out commands is performed for two command cycles; However, the use of the repetition counter reduces the time of one access to the port to the 1st cycle.
Using I / O is simplified by the fact that the input / output is also carried out, as well as memory appeal. I / O devices are displayed in the addressing / output space, using the external address of the processor and the data bus, in the same way as the memory. When addressing internal memory, the data bus is in the third state, and control signals in the passive state (high).
The interaction with memory and I / O devices at different speeds is accompanied by a ready signal. When communicating with slow devices, TMS320C2X is waiting for the device until the device completes its work and signs the processor about it through the Ready line, after which the processor will continue to work.

Central arithmetic logical device

The central arithmetic logical device (CALU) contains a 16-bit shift register, 16 x 16 parallel multiplier, 32-bit arithmetic-logical device (ALU), 32-bit battery and several additional shift registers located as at the output from the multiplier, And at the outlet of the battery.
Any ALU operation is performed in the following sequence:

1. the data is captured from the RAM to the data bus,
2. data passes through a scaling shift register and through ALU, in which arithmetic operations are performed,
3. the result is transmitted to the battery.

One input to ALU is always connected to the battery output, and the second can receive information either from the mode of the product (PR) multiplier, or boot from memory through a scaling shift register.

Conveyor operations

The command conveyor consists of a sequence of access operations to the outer bus that occur during the execution of commands. Conveyor "Predest-decoding-execution" is usually unobedient for the user, with the exception of some cases when the conveyor must be interrupted (for example, when branching). During the operation of the conveyor, the pre-election, decoding and execution of commands are independent of each other. This allows commands to overlap. So for one cycle, two or three teams can be active, each at different stages of work. Therefore, it turns out a two-tier conveyor for TMS32020 and three-level for TMS320C25.
The number of levels of the conveyor does not always affect the speed of command execution. Most commands are performed in the same number of cycles, regardless of which commands are selected from the memory: external, internal RAM or internal ROM.
The supplement hardware existing on the TMS320C25 processor allows you to expand the number of conveyor levels to three, which increases the processor performance. These funds include pre-gravating counter (PFC), 16-bit microwave stack (MCS), command register (IR), and command queue register (QIR).
With a three-level PFC conveyor contains the address of the next command to be prepriced. As soon as the prefraction is carried out, the team is loaded in IR. If IR stores a command that is not yet fulfilled, the prexected command is placed in QIR. After that, PFC increases on 1. Once the current command is executed, the QIR command will be overloaded to IR, for further execution.
Command counter (PC) contains the address of the command to be completed as follows, and is not used for capture operations.
But usually the PC is used as a pointer to the current position in the program. The contents of PC increases after each command executed. When an interruption or a subroutine call occurs, the contents of the PC is placed on the stack so that in the future you can return to the desired place of the program.
Cycles of pre-grade, decoding and execution of the conveyor are independent of each other, it allows you to overlap executable commands over time. During any cycle, three commands can be simultaneously active, each at different stages of completion.